FIG. 20 illustrates a printed circuit board which uses a related technology (surface mount technology (SMT)) to mount semiconductor parts and which is referred to as a related semiconductor device I. The related semiconductor device I is characterized by its structure in which a plurality of memory packages 102 (for example, DRAM packages) and a plurality of passive parts 103 (including capacitors, resistors, and inductors) are two-dimensionally mounted in parallel around a computing processor package 101, and is used in many electronic devices.
FIG. 21 is a sectional view of a related semiconductor device II. The related semiconductor device II is characterized by its structure in which bare semiconductor chips 204 and 205 are stacked like a pyramid (bare chips are adhered to each other with the use of an adhesive film called a die attach film), respective external terminals of the bare chips are connected to external terminals of an interposer substrate 206 by wire bonding, and the entire assembly is sealed with a resin. This is a packaging technology that accomplishes a reduction in device mount area in a semiconductor device that includes a plurality of devices, and the related semiconductor device II is one of three-dimensional packaging semiconductor devices widely used in cellular phones.
FIG. 22 is a sectional view of a semiconductor device III, which is described in Japanese Unexamined Patent Application Publication (JP-A) No. 2006-190834 (Patent Document 1). The semiconductor device III is a three-dimensional packaging semiconductor device characterized in that: external terminals (pads 304) of a first semiconductor chip 301 are opposed to and connected to external terminals (pads 304) of a second semiconductor chip 302, which differs from the first semiconductor chip 301 in outer size, with bumps 303; external terminals (pads 304) of an interposer substrate (flexible circuit board 306), which has a hole 309 at its center, and external terminals (pads 304) located in the perimeter of one of the semiconductor chips that is larger in outer size (chip 301 in FIG. 22) are connected to each other with bumps 303; and the hole 309 houses the semiconductor chip that is smaller in outside size (chip 302 in FIG. 22).
FIG. 23 is a sectional view of a semiconductor device IV, which is described in Japanese Unexamined Patent Application Publication (JP-A) No. 2007-188921 (Patent Document 2). The semiconductor device IV is a three-dimensional packaging semiconductor device characterized in that: a rigid wiring board 402 and a flexible wiring board 403 are combined to create an interposer substrate; a semiconductor element (LSI 401) is mounted to each side of the interposer substrate in a portion where the rigid wiring board 402 is located; and the flexible wiring board 403 is bent to be fixed to the rear side of one of the LSIs 401 (opposite face side from the external terminal face side).